Magnetic resonance imaging ("MRI") systems of several different types are now commercially available. One exemplary type of MRI system is described in commonly-assigned U.S. Pat. Nos. 4,297,637 to Crooks et al, 4,318,043 to Crooks et al, 4,471,305 to Crooks et al, and 4,599,565 to Hoenninger et al.
A basic problem in such systems is how to communicate control signals back and forth between the various automatically controlled portions of the system. Typically, such systems include a central digital computer performing various control functions including controlling different portions of the system so that the portions work together (in the exemplary system, this central computer is provided in addition to another computer which performs image acquisition functions). It is generally desirable to connect one or more digital devices to the digital computer as "peripherals" of the computer so that the computer can directly control and interact with the devices.
For example, it is sometimes necessary to automatically, remotely tune or detune various RF circuits under stepper motor control as MRI scanning progresses and monitor the resulting reflected RF voltage/current with a reflectometer. Similarly, it may be desirable to move the platform or bed on which the patient is resting during scanning to obtain different views of internal organs--and perhaps to monitor actual bed position as the bed is moved. Increased scanning rates now make it possible to time scans relative to the patient's breathing cycle to eliminate movement artifact. For example, the patient may be asked by a technician to hold his breath, at which time the technician depresses a "breath holding switch" in the screen room. The MRI system preferably senses depression of this switch and acquires an image while the switch is depressed. Literally countless other potential applications (e.g., indicating and control functions, and especially diagnostic, fault detection, and fault recovery functions) exist which require signal communications between the central computer and peripheral devices.
Unfortunately, electronic noise is a very serious problem in MRI installations. Despite the very high RF and magnetic field levels typically used in MRI imaging for exciting the body to be imaged, the resulting response levels produced by the body are relatively small. Therefore, maintaining an acceptably high signal-to-noise ratio is often difficult--especially because of the relatively high gain "front end" amplifiers that must be used to obtain useful signal levels. Even when tuned input circuits are used to reject signal frequencies other than the frequencies of interest, wide spectrum noise emitted by a variety of common electronic devices (e.g., computers, display devices, and practically any device including digital circuitry) can seriously degrade signal-to-noise ratio and thus limit image resolution and quality.
As is well known, various precautions (some of which are rather elaborate and expensive) are typically taken to prevent noise sources from degrading the MRI process. For example, the patient, the gradient magnetic coils, and the RF generating/detecting circuitry are all typically located in a shielded "screen room" which isolates the signal detecting circuitry from external noise sources (and prevents high intensity RF energy from radiating outside of the room). The data acquisition and control computers are generally located outside of this screen room to prevent the wide spectrum noise they generate from interfering with signal detection. Individual components and subsystems are commonly enclosed in shielded, grounded metal cases, and power lines are typically shielded (both to impede the flow of high-powered RF signals and to prevent electronic noise generated by the components and subsystems from reaching the screen room detection circuitry).
However, digital circuitry operating at virtually any frequency produces wide spectrum electronic noise that can seriously degrade the MRI process if adequate precautions are not taken. Even conventional data transmitter and receiver circuitry (such as a conventional UART and associated baud rate generator) of the type typically used to connect computer input/output ports to computer peripheral devices acts as an electronic noise generator and generates too much electronic noise to be compatible with most MRI applications.
The noise problem is exacerbated by the complex data communications requirements typically found in an MRI imaging system. For example, MRI system peripherals to be connected to the central computer typically require different communications standards and protocols. Some devices may be RS-232C compatible, while others may not be. Digital protocol converters may be required to provide compatibility and permit all peripherals to be connected to the same data transmission network. These protocol converters (the most cost-effective and versatile ones of which are microprocessor-based and programmable) usually contain their own internal clock circuits and generate even more electronic noise. Electrostatic shielding can reduce but not eliminate the noise generated by such converters and associated circuitry and is generally expensive and difficult to install.
Reliability of communications is another serious problem. Extremely intense RF and magnetic fields typically exist in the MRI screen room. These fields can generate currents on data cabling which causes "glitches" in the data being transferred. A communications network suitable for use in MRI systems must function reliably even when such fields are present.
Because of the noise and reliability problems associated with placing additional digital control circuitry in the screen room, many in the past have simply refrained from providing such additional circuitry in the first place (thus foregoing the improved system performance and functions that might be provided through additional automation). A "quiet", cost-effective digital communications network that can be used to provide reliable communications between a control computer and several different peripheral devices located in an MRI screen room simply has not been available in the past.
Of course, many different types of serial data communications networks and interfaces exist for different applications. National Semiconductor has recently developed a bidirectional, high speed serial communications interface called "MICROWIRE/PLUS" for low cost interfacing between microcontrollers and external peripherals (or other microcontrollers). This interface standard uses a single 8-bit serial data input/serial data output shift register to connect a peripheral device data bus to the MICROWIRE/PLUS network. An internal or external shift clock can be selected for each network node to permit master and slave modes of operation. To transmit data over the MICROWIRE/PLUS interface, the master signals the slave over a slave interrupt port pin. When the slave responds indicating it is ready, the master generates a "shift clock" which causes 8 bits to be shifted out of its own shift register into the slave shift register (data already in the slave shift register is simultaneously shifted out to the master shift register, permitting simultaneous data reception and transmission). Both the master and the slave preferably include 16-bit CMOS HPC microcontrollers. Memory mapping permits the master and slave to directly address their respective shift registers through memory access instructions. Further information about the National Semiconductor MICROWIRE/PLUS interface may be found in National Semiconductor publications such as Applications Note "MICROWIRE/PLUS: Interface Made Easy" by Aleaf and Lazovick.
INTEL has also developed an INTEL bit bus which requires a microprocessor at each node.
However, these existing systems were not designed with the hostile environment of an MRI screen room in mind. For a data communications network to operate satisfactorily in the MRI screen room, it must suffer little or no degradation in performance when exposed to intense RF and magnetic fields--and must ideally produce no electronic noise whatsoever during the time an MRI image is being acquired. In addition, a suitable MRI data communications network should be capable of connecting many different types of peripheral devices to the same computer, and should provide sufficient versatility to permit different communications associated with different types of peripheral devices to be communicated.
The MRI data communications network provided by the present invention has been designed with characteristics ideal for low noise operation and low cost at speeds as high as 1 Mbytes/sec and provides a serial data bus for performing medium speed control and data acquisition functions in MRI systems.
Some of the significant advantageous features of the MRI serial communications system provided by the preferred embodiment of the present invention include:
typical bus node configuration of 20 I/O data bits with address decode, parity and latched data output register in a 4-chip set; PA1 maximum speed of 1 Mbits/sec; PA1 bus node interrupt to host support; PA1 clock and data lines are not active when the bus is not in use; PA1 no local oscillator is required at bus nodes; PA1 bus may be transmitted by dual bidirectional fiber optical cables or four twisted pair cable with mixed cable types on the same bus; PA1 up to 32 bus nodes may be connected; PA1 loop back of data and clock signals are provided for high reliability; PA1 the bus is automatically self-configuring with no fixed order of nodes on the bus being required; PA1 the host has control of node disconnect (using built-in bypass mode at each bus node) for diagnostic support; PA1 reduced or expanded configurations for a node are supported, so that length of messages sent to and received from nodes can be customized on a node-by-node basis; PA1 low active device count in the node interface for low power consumption and higher reliability; PA1 low cost per bus node; and PA1 applications include remote RF coil tuning, patient bed position monitoring, breath hold image triggering, and automatic system hardware fault detection, diagnosis and logging.
The present invention provides a communications system architecture that is extremely versatile and also low in cost. In the preferred embodiment, each node of the communications system is provided with an interface implemented with electronically programmable array logic (EPLD) applications specific integrated circuits (ASIC) with 1800 equivalent gates per CMOS integrated circuit. The resulting chip set is self clocking (no local oscillator is required) and nominally provides 20 bits of latched output and input with parity checking in a four-chip set configuration. A minimal two-chip set configuration can be used for nodes that need only 4 bits of latched input and output data (while still supporting parity checking). If more than 20 bits of data input or data output are required, additional chips can be provided to increase data input and/or data output in 16-bit increments. The resulting node architecture provided by the present invention is thus easily expandable and customizable to the specific peripheral devices being connected.
In accordance with an important low noise feature of the present invention, the bus clock synchronization loop is active only when the bus host is actively sending and receiving data, and nodes on the bus require no internal clock circuits. Thus, the bus is entirely "silent" unless data is actually being transmitted and received (data transmission can be inhibited during image acquisition).
In accordance with another advantageous feature of the present invention, bus nodes may issue an interrupt request to the bus host when the clock loop is inactive--thereby initiating a message transfer.
In accordance with a further feature provided by the present invention, each bus node includes an input (to computer from node) serial data shift register and an output (from computer to node) serial data shift register--with all node shift registers connected in series to form a single, long shift register distributed along the communications network. In particular, the input of a node output shift register is connected to the output of the output shift register of the "previous" (closer to computer) node on the bus, and the output of the node output shift register is connected to the input of the output shift register of the "next" node (further away from the computer) on the bus. Similarly, the input of a node input shift register is connected to the output of the input shift register of the "next" node on the bus, and the output of the node input shift register is connected to the input of the "previous" node input shift register. The "last" node on the bus is "looped back", with the output of its output shift register connected to the input of its input register. This architecture is expandable, since any arbitrary number of nodes may be so connected. High reliability is achieved because all data signals are communicated within a closed loop.
In accordance with the another feature provided by the present invention, clock signals used for controlling the node shift registers originate at the bus host, are sent out on the bus over a separate clock loop, "loop back" at the last bus node, and return to the bus host. Significantly, the clock pulses travel around the bus in a direction opposite to the direction data pulses travel. That is, the input shift register of the "first" node on the bus receives the clock signal first--this same input shift register being the register which outputs bits of data to the central computer. This feature of the invention insures that data is stable and present at the input of any given node shift register by the time the clock pulse reaches that shift register. Two different clock pulse widths are used in the preferred embodiment one to signal data shift and the other to signal data load. The bus host sends out a clock pulse trailing edge only after it receives a looped back clock pulse leading edge, and doesn't send out a further data pulse unless it properly receives the looped back clock pulse. This loop back feature assures that all nodes are reliably clocked even when the system is exposed to high intensity RF or magnetic fields--since each node is guaranteed to have received a proper clock pulse if a proper looped back clock pulse is received by the bus host.
In accordance with yet another feature provided by the present invention, the serial communications bus is self-configuring. Each type of bus node is provided with a unique identification number. When the host computer initiates the serial bus, the host transmits a null buffer out over the bus and reads the data packets received in response. Each data packet returned to the host computer contains the identification of the node originating it and the packet length required by the node, so that the host can determining the identity, packet length, and relative positions of each node connected on the bus and the total number of nodes on the bus. Different types and numbers of nodes may be connected along the bus in any order, and the host computer need not be programmed beforehand with the bus configuration.
Any MRI peripheral subsystem can be designed to be connected to the serial communications system provided by the present invention preferred embodiment. The type of cable connection used between the serial bus nodes can vary depending upon system requirements (although the first leg into the screen room preferably comprises two bidirectional fiber optic cables). For example, once inside the screen room, shielded twisted pair cables may be used so long as noise (e.g., from MRI RF field coils) is not excessive.